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1 ? fn6270.0 preliminary el7640a, el7641a, el7642a tft-lcd dc/dc with integrated amplifiers the el7640a, el7641a, and el7642a integrate a high performance boost regulator with 2 ldo controllers for v on and v off , a v on -slice circuit with adjustable delay and either one (el7640a), three (el7641a), or five amplifiers (el7642a) for v com and v gamma applications. the boost converter in the el7640a, el7641a, and el7642a is a current mode pwm type integrating an 18v nhchannel mosfet. operating at 1.2mhz, this boost can operate in either p-mode for su perior transient response, or in pi-mode for tighter output regulation. using external low-cost transistors, the ldo controllers provide tight regulation for v on , v off , as well as providing start-up sequence control and fault protection. the amplifiers are ideal for v com and v gamma applications, with 150ma peak output current drive, 12mhz bandwidth, and 12v/ s slew rate. all inputs and outputs are rail-to-rail. available in the 32 ld thin qfn (5mm x 5mm) pb-free packages, the el7640a, el7641a, and el7642a are specified for operation over the -40c to +85c temperature range. features ? current mode boost regulator - fast transient response - 1% accurate output voltage - 18v/3a integrated fet - >90% efficiency ? 2.6v to 5.5v v in supply ? 2 ldo controllers for v on and v off - 2% output regulation -v on -slice circuit ? high speed amplifiers - 150ma short-circuit output current -12v/ s slew rate - 12mhz -3db bandwidth - rail-to-rail inputs and outputs ? built-in power sequencing ? internal soft-start ? multiple overload protection ? thermal shutdown ? 32 ld 5x5 thin qfn package ? pb-free plus anneal available (rohs compliant) applications ? tft-lcd panels ? lcd monitors ? notebooks ?lcd-tvs ordering information part number (note) part marking tape & reel package (pb-free) pkg. dwg. # el7640ailtz 7640ailtz - 32 ld 5x5 thin qfn mdp0051 EL7640AILTZ-T7 7640ailtz 7? 32 ld 5x5 thin qfn mdp0051 el7640ailtz-t13 7640ailtz 13? 32 ld 5x5 thin qfn mdp0051 el7641ailtz 7641ailtz - 32 ld 5x5 thin qfn mdp0051 el7641ailtz-t7 7641ailtz 7? 32 ld 5x5 thin qfn mdp0051 el7641ailtz-t13 7641ailtz 13? 32 ld 5x5 thin qfn mdp0051 el7642ailtz 7642ailtz - 32 ld 5x5 thin qfn mdp0051 el7642ailtz-t7 7642ailtz 7? 32 ld 5x5 thin qfn mdp0051 el7642ailtz-t13 7642ailtz 13? 32 ld 5x5 thin qfn mdp0051 note: intersil pb-free plus anneal produc ts employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb -free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet may 15, 2006 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6270.0 may 15, 2006 pinouts el7640a (32 ld qfn) top view el7641a (32 ld qfn) top view el7642a (32 ld qfn) top view nc = not internally connected ic = internally connected thermal pad 24 23 22 21 20 19 18 32 31 30 29 28 10 11 12 13 14 1 2 3 4 5 6 7 8 17 15 27 16 26 9 25 src ref agnd pgnd out1 neg1 pos1 nc nc ic bgnd nc nc sup nc nc comp fb in lx nc nc ic nc fbp com drn ctl del drvn fbn drvp nc = not internally connected ic = internally connected thermal pad 24 23 22 21 20 19 18 32 31 30 29 28 10 11 12 13 14 1 2 3 4 5 6 7 8 17 15 27 16 26 9 25 src ref agnd pgnd out1 neg1 pos1 out2 neg2 pos2 bgnd nc nc sup pos3 neg3 comp fb in lx nc nc ic out3 fbp com drn ctl del drvn fbn drvp thermal pad 24 23 22 21 20 19 18 32 31 30 29 28 10 11 12 13 14 1 2 3 4 5 6 7 8 17 15 27 16 26 9 25 src ref agnd pgnd out1 neg1 pos1 out2 neg2 pos2 bgnd pos3 out3 sup pos4 neg4 comp fb in lx out5 neg5 pos5 out4 fbp com drn ctl del drvn fbn drvp el7640a, el7641a, el7642a
3 fn6270.0 may 15, 2006 absolute maxi mum ratings (t a = 25c) in, ctl to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v comp, fb, fbp, fbn, del, ref to agnd. . . . . -0.3v to v in +0.3v pgnd, bgnd to agnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3v lx to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +24v sup to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +18v drvp, src to agnd . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +36v pos1, neg1, out1, pos2, neg2, out2, pos3, out3, pos4, neg4, out4, pos5, out5 to agnd . . -0.3v to v sup +0.3v drvn to agnd . . . . . . . . . . . . . . . . . . . . . . . v in -20v to v in +0.3v com, drn to agnd . . . . . . . . . . . . . . . . . . . . -0.3v to v src +0.3v lx maximum continuous rms output current. . . . . . . . . . . . . 1.6a out1, out2, out3, out4, out5 maximum continuous output current . . . . . . . . . . . . . . . . . . 75ma storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c maximum continuous junction temperature . . . . . . . . . . . . +125c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves operating ambient temperature . . . . . . . . . . . . . . . .-40c to +85c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v in = 3v, v boost = v sup = 12v, v src = 20v, over temperature from -40c to 85c. unless otherwise specified. parameter description conditions min typ max unit supply v in input supply range 2.6 5.5 v v lor undervoltage lockout threshold v in rising 2.4 2.5 2.6 v v lof undervoltage lockout threshold v in falling 2.2 2.3 2.4 v i s quiescent current lx not switching 2.5 ma i ss quiescent current - switching lx switching 5 10 ma t fd fault delay time c del = 100nf 23 ms v ref reference voltage t a = 25c 1.19 1.215 1.235 v 1.187 1.215 1.238 v shutdn thermal shutdown temperature 140 c main boost regulator v boost output voltage range (note 1) v in + 15% 18 v f osc oscillator frequency 1050 1200 1350 khz d cm maximum duty cycle 82 85 % v fbb boost feedback voltage t a = 25c 1.192 1.205 1.218 v 1.188 1.205 1.222 v v ftb fb fault trip level falling edge 0.85 0.925 1.020 v ? v boost / ? i boost load regulation 50ma < i load < 250ma 0.1 % ? v boost / ? v in line regulation v in = 2.6v to 5.5v 0.08 %/v i fb input bias current v fb = 1.35v 500 na gmv fb transconductance di = 2.5a at comp, fb = comp 160 a/v r on lx lx on resistance 160 m ? i leak lx lx leakage current v fb = 1.35v, v lx = 13v 0.02 40 a i lim lx lx current limit duty cycle = 65% (note 1) 3.0 a t ss b soft-start period c del = 100nf 7 ms el7640a, el7641a, el7642a
4 fn6270.0 may 15, 2006 operational amplifiers v sup supply operating range 4.5 18 v i sup supply current per amplifier 600 800 a v os offset voltage 312mv i b input bias current -50 +50 na cmir common mode input range 0 v sup v cmrr common mode rejection ratio 60 90 db a ol open loop gain 110 db v oh output voltage high i out = 100a v sup -15 v sup -2 mv i out = 5ma v sup -250 v sup -150 mv v ol output voltage low i out = -100a 2 30 mv i out = -5ma 100 150 mv i sc short-circuit current 100 150 ma i cont continuous output current 50 ma psrr power supply rejection ratio 60 100 db bw -3db -3db bandwidth 12 mhz gbwp gain bandwidth product 8mhz sr slew rate 12 v/s positive ldo v fbp positive feedback voltage i drvp = 100a, t a = 25c 1.176 1.2 1.224 v i drvp = 100a 1.176 1.2 1.229 v v ftp v fbp fault trip level v fbp falling 0.82 0.9 0.98 v i bp positive ldo input bias current v fbp = 1.4v -50 50 na ? v pos / ? i pos fbp load regulation v drvp = 25v, i drvp = 0 to 20a 0.5 % i drvp sink current v fbp = 1.1v, v drvp = 10v 2 4 ma i leak p drvp off leakage current v fbp = 1.4v, v drvp = 30v 0.1 10 a t ss p soft-start period c del = 100nf 7 ms negative ldo v fbn fbn regulation voltage i drvn = 0.2ma, t a = 25c 0.173 0.203 0.233 v i drvn = 0.2ma 0.171 0.203 0.235 v v ftn v fbn fault trip level v fbn rising 380 430 480 mv i bn negative ldo input bias current v fbn = 250mv -50 50 na fbn load regulation v drvn = -6v, i drvn = 2a to 20a 0.5 % i drvn source current v fbn = 500mv, v drvn = -6v 2 4 ma i leak n drvn off leakage current v fbp = 1.35v, v drvp = 30v 0.1 10 a t ss n soft-start period c del = 100nf 7 ms electrical specifications v in = 3v, v boost = v sup = 12v, v src = 20v, over temperature from -40c to 85c. unless otherwise specified. (continued) parameter description conditions min typ max unit el7640a, el7641a, el7642a
5 fn6270.0 may 15, 2006 v on -slice circuit v lo ctl input low voltage v in = 2.6v to 5.5v 0.4v in v v hi ctl input high voltage v in = 2.6v to 5.5v 0.6v in v i leak ctl ctl input leakage current ctl = agnd or in -1 1 a t d rise ctl to out rising prop delay 1k ? from drn to 8v, v ctl = 0v to 3v step, no load on out, measured from v ctl = 1.5v to out = 20% 100 ns t d fall ctl to out falling prop delay 1k ? from drn to 8v, v ctl = 3v to 0v step, no load on out, measured from v ctl = 1.5v to out = 80% 100 ns v src src input voltage range 30 v isrc src input current start-up sequence not completed 150 250 a start-up sequence completed 150 250 a r on src src on resistance start-up sequence completed 5 10 ? r on drn drn on resistance start-up sequence completed 30 60 ? r on com com to gnd on resistance start-up sequence not completed 350 1000 1800 ? sequencing t on turn on delay c del = 100nf (see figure 23) 10 ms t del1 delay between v boost and v off c del = 100nf (see figure 23) 10 ms t del2 delay between v on and v off c del = 100nf (see figure 23) 10 ms t del3 delay from v on to v on -slice enabled c del = 100nf (see figure 23) 10 ms c del delay capacitor 22 100 nf note: 1. guaranteed by design. electrical specifications v in = 3v, v boost = v sup = 12v, v src = 20v, over temperature from -40c to 85c. unless otherwise specified. (continued) parameter description conditions min typ max unit el7640a, el7641a, el7642a
6 fn6270.0 may 15, 2006 pin descriptions pin name el7642a el7641a el7640a pin function src 1 1 1 upper reference voltage for switch output ref 2 2 2 internal reference bypass terminal agnd 3 3 3 analog ground for boost converter and control circuitry pgnd 4 4 4 power ground for boost switch out1 5 5 5 operational amplifier 1 output neg1 6 6 6 operational amplifier 1 inverting input pos1 7 7 7 operational amplifier 1 non-inverting input out2 8 8 - operational amplifier 2 output neg2 9 9 - operational amplifier 2 inverting input pos2 10 10 - operational amplifier 2 non-inverting input bgnd 11 11 11 operational amplifier ground pos3 12 15 - operational amplifier 3 non-inverting input neg3 - 16 - operational amplifier 3 inverting input out3 13 17 - operational amplifier 3 output sup 14 14 14 amplifier positive supply rail. bypass to bgnd with 0.1f capacitor pos4 15 - - operational amplifier 4 non-inverting input neg4 16 - - operational amplifier 4 inverting input out4 17 - - operational amplifier 4 output pos5 18 - - operational amplifier 5 non-inverting input neg5 19 - - operational amplifier 5 inverting input out5 20 - - operational amplifier 5 output lx 21 21 21 main boost regulator switch connection in 22 22 22 main supply input; bypass to agnd with 1f capacitor fb 23 23 23 main boost feedback voltage connection comp 24 24 24 error amplifier compensation pin fbp 25 25 25 positive ldo feedback connection drvp 26 26 26 positive ldo transistor drive fbn 27 27 27 negative ldo feedback connection drvn 28 28 28 negative ldo transistor driver del 29 29 29 connection for switch delay timing capacitor ctl 30 30 30 input control for switch output drn 31 31 31 lower reference voltage for switch output com 32 32 32 switch output; when ctl = 1, com is connected to src through a 15 ? resistor; when ctl = 0, com is connected to drn through a 30 ? resistor el7640a, el7641a, el7642a
7 fn6270.0 may 15, 2006 typical performance curves figure 1. boost efficiency at v out = 12v (pi mode) figure 2. boost efficiency at v out = 12v (p mode) figure 3. boost load regulation vs load current (pi mode) figure 4. boost load regulation vs load current (p mode) figure 5. boost line regu lation vs input voltage (pi mode) figure 6. boost line regu lation vs input voltage (p mode) 0 10 20 30 40 50 60 70 80 90 100 efficiency (%) 0 200 400 600 800 1000 1200 load current (ma) v in =5v v in =3v efficiency (%) 78 80 82 84 86 88 90 92 94 0 200 400 600 800 1000 1200 load current (ma) v in =5v v in =3v load regulation (%) -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0 200 400 600 800 1000 1200 load current (ma) v in =5v v in =3v load regulation (%) -14 -12 -10 -8 -6 -4 -2 0 0 200 400 600 800 1000 1200 load current (ma) v in =3.3v v in =5.0v 0 0.02 0.04 0.06 0.08 0.1 0.12 3 3.5 4 4.5 5 5.5 6 input voltage (v) line regulation (%) 0.5 0 1 1.5 2 2.5 3.5 33.544.555.56 input voltage (v) line regulation (%) 3 el7640a, el7641a, el7642a
8 fn6270.0 may 15, 2006 figure 7. boost pulse load transient response figure 8. v on load regulation figure 9. v on line regulation figure 10. v off load regulation figure 11. v off line regulation figure 12. start-up sequence typical performance curves (continued) boost output (ac coupling) v boost =12v c out =30f voltage boost output current -0.25 -0.2 -0.15 -0.1 -0.05 0 5 1015202530 v on load current (ma) load regulation (%) v on =20v -0.12 -0.1 -0.08 -0.06 -0.04 -0.02 0 20 21 22 23 24 25 26 input voltage (v) line regulation (%) v on =20v i load =20ma -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 5 1015202530 load current (ma) load regulation (%) v off =-8v -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 -15-14-13-12-11-10 input voltage (v) line regulation (%) v off =-8v i load =50ma time (20ms/div) v cdel v boost v off v on el7640a, el7641a, el7642a
9 fn6270.0 may 15, 2006 applications information the el7640a, el7641a, el7642a provide a highly integrated multiple output power solution for tft-lcd applications. the system consists of one high efficiency boost converter and two low cost linear-regulator controllers (v on and v off ) with multiple protec tion functions. the block diagram of the whole part is shown in figure 17. table 1 lists the recommended components. the el7640a, el7641a, el7642a integrate an n-channel mosfet in boost converter to minimize the external component counts and cost. the v on , v off linear- regulators are independently r egulated by using external resistors. to achieve higher voltage than v boost , one or multiple stage charge pumps may be used. figure 13. start-up sequence figure 14 . op amp rail-to-rail input/output figure 15. package power dissipation vs ambient temperature figure 16. package power dissipation vs ambient temperature typical performance curves (continued) time (20ms/div) input voltage v boost v off v on input output time (50s/div) jedec jesd51-3 and semi g42-88 (single layer) test board 0.8 0.7 0.5 0.3 0.2 0.1 0 0 255075100 150 ambient temperature (c) power dissipation (w) 125 85 0.6 0.4 ja =125c/w qfn32 758mw jedec jesd51-7 high effective thermal conductivity test board - qfn exposed diepad soldered to pcb per jesd51-5 3 2.5 2 1.5 1 0.5 0 0 255075100 150 ambient temperature (c) power dissipation (w) 2.857w ja =35c/w qfn32 125 85 table 1. recommended components designation description c 1 , c 2 , c 3 10f, 16v x5r ceramic capacitor (1210) tdk c3216x5r0j106k d 1 1a 20v low leakage schottky rectifier (case 457-04) on semi mbrm120et3 d 11 , d 12 , d 21 200ma 30v schottky barrier diode (sot-23) fairchild bat54s l 1 6.8h 1.3a inductor tdk slf6025t-6r8m1r3-pf q 11 200ma 40v pnp amplifier (sot-23) fairchild mmbt3906 q 21 200ma 40v npn amplifier (sot-23) fairchild mmbt3904 el7640a, el7641a, el7642a
10 fn6270.0 may 15, 2006 figure 17. block diagram boost converter the main boost converter is a current mode pwm converter operating at a fixed frequency. the 1.2mhz switching frequency enables the use of low profile inductor and multilayer ceramic capacitors, which results in a compact, low cost power system for lcd panel design. the boost converter can operate in continuous or discontinuous inductor current mode. the el7640a, el7641a, el7642a are designed for continuous current mode, but they can also operate in discontinuous current mode at light load. in continu ous current mode, current flows continuously in the inductor du ring the entire switching cycle in steady state operation. the voltage conversion ratio in continuous current mode is given by: where d is the duty cycle of switching mosfet. figure 18 shows the block diagram of the boost controller. it uses a summing amplifier architecture consisting of gm stages for voltage feedback, current feedback and slope compensation. a comparator l ooks at the peak inductor current cycle by cycle and term inates the pwm cycle if the current limit is reached. an external resistor divider is required to divide the output voltage down to the nominal reference voltage. current drawn by the resistor network should be limited to maintain the overall converter efficienc y. the maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. a resistor network in the order of 60k ? is recommended. the boost converter output vo ltage is determined by the following equation: pwm logic controller buffer oscillator slope compensation osc reference generator v ref gm amplifier uvlo comparator voltage amplifier current amplifier thermal shutdown ss + - uvlo comparator buffer uvlo comparator ss + - shutdown & start-up control buffer fbp drvp fbb c int drvn fbn 0.4v 0.2v v ref comp current limit comparator current ref pgnd lx v boost v in ----------------------- - 1 1d ? ------------- = v boost r 1 r 2 + r 1 -------------------- - v ref = el7640a, el7641a, el7642a
11 fn6270.0 may 15, 2006 the current through mosfet is limited to 3a peak. this restricts the maximum output current based on the following equation: where ? i l is peak to peak inductor ripple current, and is set by: where f s is the switching frequency. figure 18. the block diagram of the boost controller i omax i lmt ? i l 2 -------- ? ?? ?? v in v o --------- = ? i l v in l --------- d f s ---- - = i ref i ref fbb i fb i fb comp voltage amplifier lx pgnd shutdown & start-up control gm amplifier slope compensation buffer pwm logic current amplifier clock reference generator el7640a, el7641a, el7642a
12 fn6270.0 may 15, 2006 the following table gives typical values (margins are considered 10%, 3%, 20%, 10% and 15% on v in , v o , l, f s and i lmt : input capacitor the input capacitor is used to supply the current to the converter. it is recommended that c in be larger than 10 f. the reflected ripple voltage will be smaller with larger c in . the voltage rating of input capacitor should be larger than maximum input voltage. boost inductor the boost inductor is a critical part which influences the output voltage ripple, transient response, and efficiency. value of 3.3 h to 10 h inductor is recommended in applications to fit the intern al slope compensation. the inductor must be able to handle the following average and peak current: rectifier diode a high-speed diode is desired due to the high switching frequency. schottky diodes are recommended because of their fast recovery time and low forward voltage. the rectifier diode must meet the output current and peak inductor current requirements. output capacitor the output capacitor supplies the load directly and reduces the ripple voltage at the output. output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the esr of output capacitor, and the charging an d discharging of the output capacitor. for low esr ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. the voltage rating of the output capacitor should be greater than the maximum output voltage. note: capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. c out in the equation above assumes the effective value of the capacitor at a particular voltage and not the manufacturer?s stated value, measured at zero volts. compensation the el7640a, el7641a, el7642a can operate in either p mode or pi mode. connecting comp pin directly to v in will enable p mode; for better load regulation, use pi mode with a 2.2nf capacitor and a 180 ? resistor in series between comp pin and ground. to impr ove the transient response, either the resistor value can be increased or the capacitor value can be reduced, but too high resistor value or too low capacitor value will reduce loop stability. boost feedback resistors as the boost output voltage, v boost , is reduced below 12v the effective voltage feedback in the ic increases the ratio of voltage to current feedback at the summing comparator because r2 decreases relative to r1. to maintain stable operation over the complete current range of the ic, the voltage feedback to the fbb pin should be reduced proportionally, as v boost is reduced, by means of a series resistor-capacitor network (r7 and c7) in parallel with r1, with a pole frequency (fp) set to approximately 10khz. for c2 effective = 10f and 4khz for c2 (effective) = 30f. r7 = ((1/0.1 x r2) ? 1/r1)^-1 c7 = 1/(2 x 3.142 x fp x r7) linear-regulator controllers (v on and v off ) the el7640a, el7641a, el7642a include 2 independent linear-regulator controllers, in which there is one positive output voltage (v on ), and one negative voltage (v off ). the v on and v off linear-regulator controller function diagram, application circuit and waveforms are shown in figure 19 and figure 20 respectively. table 2. v in (v) v o (v) l (h) f s (mhz) i omax (ma) 3.3 9 6.8 1.2 898 3.3 12 6.8 1.2 622 3.3 15 6.8 1.2 458 5 9 6.8 1.2 1360 5126.81.2 944 5156.81.2 694 i lavg i o 1d ? ------------- = i lpk i lavg ? i l 2 -------- + = v ripple i lpk esr v o v in ? v o ----------------------- - i o c out --------------- - 1 f s ---- - + = el7640a, el7641a, el7642a
13 fn6270.0 may 15, 2006 figure 19. v on functional block diagram figure 20. v off functional block diagram the v on power supply is used to power the positive supply of the row driver in the lcd pa nel. the dc/dc consists of an external diode-capacitor c harge pump powered from the inductor (lx) of the boost converter, followed by a low dropout linear regulator (ldo_on). the ldo_on regulator uses an external pnp transistor as the pass element. the onboard ldo controller is a wide band (>10mhz) transconductance amplifier ca pable of 5ma output current, which is sufficient for up to 50ma or more output current under the low dropout condition (forced beta of 10). typical v on voltage supported by el7640a, el7641a and el7642a ranges from +15v to +36v. a fault comparator is also included for monitoring the output voltage. the under- voltage threshold is set at 25% below the 1.2v reference. the v off power supply is used to power the negative supply of the row driver in the lcd panel. the dc/dc consists of an external diode-capacitor charge pump powered from the inductor (lx) of the boost converter, followed by a low dropout linear regulator (ldo_off). the ldo_off regulator uses an external npn transistor as the pass element. the onboard ldo controller is a wide band (>10mhz) transconductance amplifier capable of 5ma output current, which is sufficie nt for up to 50ma or more output current under the low dropout condition (forced beta of 10). typical v off voltage supported by el7640a, el7641a and el7642a ranges from -5v to -25v. a fault comparator is also included for monitoring the output voltage. the under-voltage threshold is set at 200mv above the 0.2v reference level. set-up output voltage refer to typical application diagram , the output voltages of v on , v off and v logic are determined by the following equations: where v ref = 1.2v, v refn = 0.2v. high charge pump ou tput voltage (>36v) applications in the applications where the charge pump output voltage is over 36v, an external npn transistor needs to be inserted in between the drvp pin and the base of pass transistor q3 as shown in figure 21, or the linear regulator can control only one stage charge pump and regulate the final charge pump output as shown in figure 22. - + - + 36v esd clamp gmp ldo_on pg_ldop 1: np fbp drvp 700 ? r bp v boost 0.1f 0.1f cp (to 36v) 20k ? r p2 r p1 c on v on (to 35v) lx 0.9v - + - + 36v esd clamp gmn ldo_off 1: nn fbn drvn 0.1f 0.1f cp (to -26v) r bn c off v off (to -20v) lx r n1 r n2 20k ? v ref pg_ldon 0.4v 700 ? v on v ref 1 r 12 r 11 --------- - + ?? ?? ?? = v off v refn r 22 r 21 --------- - v refn v ref ? () + = v in or v boost charge pump output 700 ? q11 fbp drvp npn cascode transistor el764x v on figure 21. cascode npn transistor configuration for high charge pump output voltage (>36v) el7640a, el7641a, el7642a
14 fn6270.0 may 15, 2006 calculation of the linear regulator base-emitter resistors (rbp and rbn) for the pass transistor of the linear regulator, low frequency gain (hfe) and unity gain frequency (f t ) are usually specified in the datasheet. the pass transistor adds a pole to the loop transfer function at fp = f t /hfe. therefore, in order to maintain phase margin at low frequency, the best choice for a pass device is often a high frequency low gain switching transistor. further improvement can be obtained by adding a base-emitter resistor r be (r bp , r bl , r bn in the functional block diagram), which increases the pole frequency to: fp = ft*(1+ hfe *re/r be )/hfe, where re = kt/qic. so choose the lowest value r be in the design as long as there is still enough base current (i b ) to support the maximum output current (i c ). we will take as an example the v on linear regulator. if a fairchild mmbt3906 pnp transistor is used as the external pass transistor, q11 in the application diagram, then for a maximum v on operating requirement of 50ma the data sheet indicates hfe_min = 60. the base-emitter saturation voltage is: vbe_max = 0.7v. for the el7640a, el7641a and el7642a, the minimum drive current is: i_drvp_min = 2ma the minimum base-emitter resistor, rbp, can now be calculated as: rbp_min = vbe_max/(i_dr vp_min - ic/hfe_min) = 0.7v/(2ma - 50ma/60) = 600 ? this is the minimum value that can be used ? so, we now choose a convenient value grea ter than this minimum value; say 700 ? . larger values may be used to reduce quiescent current, however, regulation may be adversely affected by supply noise if r bp is made too high in value. charge pump to generate an output voltage higher than v boost , single or multiple stages of charge pumps are needed. the number of stage is determined by the input and output voltage. for positive charge pump stages: where v ce is the dropout voltage of the pass component of the linear regulator. it ranges from 0.3v to 1v depending on the transistor selected. v f is the forward-voltage of the charge-pump rectifier diode. the number of negative charge -pump stages is given by: to achieve high efficiency and low material cost, the lowest number of charge-pump stages, which can meet the above requirements, is always preferred. charge pump output capacitors ceramic capacitor with low esr is recommended. with ceramic capacitors, the output ripple voltage is dominated by the capacitance value. the capacitance value can be chosen by the following equation: where f osc is the switching frequency. discontinuous/continuous boost operation and its effect on the charge pumps the el7640a, el7641a and el7642a v on and v off architecture uses lx switching edges to drive diode charge pumps from which ldo regulators generate the v on and v on (>36v) 0.1f 0.1f 0.1f 0.1f 0.47f 0.22f 700 ? 0.1f v boost lx q11 fbp drvp el7642a figure 22. the linear regulator controls one stage of charge pump n positive v out v ce v input ? + v input 2v f ? ------------------------------------------------------------- - n negative v output v ce + v input 2v f ? ------------------------------------------------ - c out i out 2v ripple f osc ------------------------------------------------------ el7640a, el7641a, el7642a
15 fn6270.0 may 15, 2006 v off supplies. it can be apprecia ted that should a regular supply of lx switching edge s be interrupted, for example during discontinuous operation at light boost load currents, then this may affect the performance of v on and v off regulation ? depending on their exact loading conditions at the time. to optimize v on /v off regulation, the boundary of discontinuous/continuous operation of the boost converter can be adjusted, by suitable choice of inductor given v in , v out , switching frequency and the v boost current loading, to be in continuous operation. the following equation gives the boundary between discontinuous and continuous boost operation. for continuous operation (lx switching every clock cycle) we require that: i(v boost _load) > d*(1-d)*v in /(2*l*f osc ) where the duty cycle, d = (v boost ? v in )/v boost for example, with v in = 5v, f osc = 1.2mhz and v boost = 12v we find continuous operation of the boost converter can be guaranteed for: l = 10h and i(v boost ) > 51ma l = 6.8h and i(v boost ) > 74ma l = 3.3h and i(v boost ) > 153ma start-up sequence figure 23 shows a detailed start-up sequence waveform. for a successful power-up, there should be 6 peaks at v cdel . when a fault is detected, the device will latch off until either en is toggled or the input supply is recycled. when the input voltage is higher than 2.4v, an internal current source starts to charge c cdel . during the initial slow ramp, the device checks whether there is a fault condition. if no fault is found during the initial ramp, c cdel is discharged after the first peak. v ref turns on at the peak of the first ramp. initially the boost is not enabled so v boost rises to v in - v diode through the output diode. h ence, there is a step at v boost during this part of the start-up sequence. v boost soft-starts at the beginning of the third ramp, and is checked at the end of this ramp. the soft-start ramp depends on the value of the c del capacitor. for c del of 100nf, the soft-start time is ~7ms. v off turns on at the start of the fourth peak. v on is enabled at the beginning of the sixth ramp. v off and v on are checked at end of this ramp. el7640a, el7641a, el7642a
16 fn6270.0 may 15, 2006 component selection for start-up sequencing and fault protection the c ref capacitor is typically set at 220nf and is required to stabilize the v ref output. the range of c ref is from 22nf to 1f and should not be more than five times the capacitor on c del to ensure correct start-up operation. the c del capacitor is typically 100nf and has a usable range from 22nf minimum to several microfarads ? only limited by the leakage in the capacitor reaching a levels. c del should be at least 1/5 of the value of c ref (see above). note that with 100nf on c del the fault time-out will be typically 23ms and the use of a larger/smaller value will vary this time proportionally (e.g. 1f will give a fault time- out period of typically 230ms). fault sequencing the el7640a, el7641a and el7642a have an advanced fault detection system which protects the ic from both adjacent pin shorts during operation and shorts on the output v cdel in v ref v boost v off v on v ref on v boost soft-start v off on v on soft-start fault detecte d chip disabled normal operation fault present start-up sequence timed by c del t on t del1 t del2 t del3 v on slice circuit figure 23. start-up sequence note: not to scale el7640a, el7641a, el7642a
17 fn6270.0 may 15, 2006 supplies. a high quality layout/des ign of the pcb, in respect of grounding quality and decoupling is necessary to avoid falsely triggering the fault detection scheme ? especially during start-up. the user is dire cted to the layout guidelines and component selection sections to avoid problems during initial evaluation and prototype pcb generation. v on -slice circuit the v on -slice circuit func tions as a three way multiplexer, switching the voltage on com between ground, drn and src, under control of the start-up sequence and the ctl pin. during the start-up sequence, com is held at ground via an ndmos fet, with ~1k impedance. once the start-up sequence has completed, ctl is enabled and acts as a multiplexer control such that if ctl is low, com connects to drn through a 5 ? internal mosfet, and if ctl is high, com connects to src via a 30 ? mosfet. the slew rate of start-up of the switch control circuit is mainly restricted by the load capacitance at com pin as in the following equation: where v g is the supply voltage applied to the switch control circuit, r i is the resistance between com and drn or src including the internal mosfet r ds(on) , the trace resistance and the resistor inserted, r l is the load resistance of the switch control circuit, and c l is the load capacitance of the switch control circuit. in the typical application circuit, r 8 , r 9 and c 8 give the bias to drn based on the following equation: and r 10 can be adjusted to adjust the slew rate. op amps the el7640a, el7641a and el7642a have 1, 3 and 5 amplifiers respectively. the op amps are typically used to drive the tft-lcd backplane (v com ) or the gamma- correction divider string. they feature rail-to-rail input and output capability, they are unity gain stable, and have low power consumption (typical 600 a per amplifier). the el7640a, el7641a and el7642a have a ?3db bandwidth of 12mhz while maintaining a 10v/ s slew rate. short circuit current limit the el7640a, el7641a and el7642a will limit the short circuit current to 180ma if t he output is directly shorted to the positive or the negat ive supply. if an output is shorted for a long time, the junction temperature will trigger the over temperature protection limit and hence the part will shut down. driving capacitive loads el7640a, el7641a and el7642a can drive a wide range of capacitive loads. as load capacitance increases, however, the ?3db bandwidth of the device will decrease and the peaking will increase. the amplifiers drive 10pf loads in parallel with 10k ? with just 1.5db of peaking, and 100pf with 6.4db of peaking. if less peaking is desired in these applications, a small series resistor (usually between 5 ? and 50 ? ) can be placed in series with the output. however, this will obviously reduce the gain. another method of reducing peaking is to add a ?snubber? circuit at the output. a snubber is a shunt load consisting of a resistor in series with a capacitor. values of 150 ? and 10nf are typical. the advantage of a snubber is that it does not draw any dc load current and reduce the gain. over-temperature protection an internal temperature sens or continuously monitors the die temperature. in the event that the die temperature exceeds the thermal trip point, the device will be latched off until either the i nput supply vo ltage or enable is cycled. layout recommendation the device?s performance including efficiency, output noise, transient response and control loop stability is dramatically affected by the pcb layout. pcb layout is critical, especially at high switching frequency. there are some general guidelines for layout: 1. place the external power components (the input capacitors, output capacitors , boost inductor and output diodes, etc.) in close proximity to the device. traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. place v ref and v dd bypass capacitors close to the pins. 3. reduce the loop with large ac amplitudes and fast slew rate. 4. the feedback network should sense the output voltage directly from the point of load, and be as far away from lx node as possible. 5. the power ground (pgnd) and signal ground (sgnd) pins should be connected at only one point. 6. the exposed die plate, on the underneath of the package, should be soldered to an equivalent area of metal on the pcb. this contact area should have multiple via connections to the back of the pcb as well as connections to intermediate pcb layers, if available, to maximize thermal dissipation away from the ic. 7. to minimize the thermal resistance of the package when soldered to a multi-layer pcb, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the ic. the bottom and top pcb areas especially should be maximized to allow thermal dissipation to the surrounding air. ? v ? t ------- - v g r i r l || () c l ? ------------------------------------ = v drn v on r 9 a vdd r 8 ? + ? r 8 r 9 + ------------------------------------------------------------- = el7640a, el7641a, el7642a
18 fn6270.0 may 15, 2006 8. a signal ground plane, separate from the power ground plane and connected to the power ground pins only at the exposed die plate, should be used for ground return connections for feedback resistor networks (r1, r11, r41) and the v ref capacitor, c22, the c delay capacitor c7 and the integrator capacitor c23. 9. minimize feedback input track lengths to avoid switching noise pick-up. a demo board is available to illustrate the proper layout implementation. typical application circuit - + - + - + - + - + boost pos reg sw ctl neg reg ref v in (2.6v-5.5v) 10f in comp drvn fbn ref ctl del 100nf control input a vdd neg4 out4 pos4 neg2 out2 pos2 v com set2 v com2 v com fb2 v com set4 v com4 v com fb4 v main agnd op2 op4 pos1 v com set1 op1 op5 op3 out1 v com1 neg1 v com fb1 pos5 v com set3 out5 v com3 neg5 v com fb3 pos3 v gamma set out3 v gamma drn com r 8 68k ? c 8 0.1f r 9 1k ? a vdd src fbp drvp 700 ? 182k ? 9.76k ? 470nf 0.1f v cp v on (24.5v) gnd pgnd fb 10.2k ? 64.9k ? 10fx2 a vdd (9v) v cp 0.1f 0.1f 0.1f 0.1f l1 v cn 0.1f 470nf v neg (-8v) v cn 700 ? 82k ? 10k ? lx to gate driver ic 180 ? 2.2nf 0.1f 10 ? 470nf d11 d12 d21 c1 6.8h d1 c2 r2 r1 r12 r11 q11 q21 r22 r21 r 7 open c 7 open r 10 1k ? el7640a, el7641a, el7642a
19 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6270.0 may 15, 2006 qfn package outline drawing note: the package drawing shown here may not be the latest version. to check the latest revision, please refer to the intersil w ebsite at http://www.intersil.com/design/packages/index.asp el7640a, el7641a, el7642a

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